In semiconductor memory components in cross-point architecture, the memory cells are arranged at the crossing points of the bit lines and word lines. The bit lines are in each case arranged parallel to and at a distance from one another, and the word lines, transversely with respect to the bit lines, are likewise arranged parallel to and at a distance from one another. Each bit line crosses each word line at a location at which a respective memory cell is arranged. Resistively switching storage media are generally used for this type of architecture. The memory cell is selected by addressing the bit line and the word line which lead to the respective crossing point. The application of suitable electrical potentials to the bit lines and word lines thus makes it possible to program, read and, if appropriate, erase individual memory cells. The cross-point architecture has the advantage that the surface area taken up by each memory cell is very small.
On the other hand, what are known as disturb effects occur with a cross-point architecture, caused by the fact that during the write, erase and read operations voltages are also present at the memory cells, which have not been selected. Depending on the operating conditions, these voltages are lower by a factor of two or three than those of the selected cells. Nevertheless, during the read operation, for example, the unselected cells may make significant contributions to the flow of current, making it more difficult or even impossible to evaluate the programmed state of the selected cell.
FIG. 5 illustrates how this effect comes about, representing an excerpt from an array of resistive memory cells in rows and columns, which are addressed via word lines and bit lines. In this example, it has been assumed that the memory cell 15 is being addressed via the selected bit line 10 and the selected word line 20. The further memory cell 18 connected to the selected bit line 10 connects the selected bit line 10 to the unselected word line 21, which is connected to the unselected bit line 11 via the further memory cell 17. The unselected bit line 11 for its part is connected to the selected word line 20 via the further memory cell 14, so that a flow of current via the current path 8 indicated by dashed lines contributes to the overall flow of current between the selected lines 10 and 20. A similar state of affairs also applies to the other memory cells of the array that are not directly connected to the selected lines. By way of example, a current flows between the selected lines 10 and 20 via the further memory cells 14, 12 and 13 and 16, 19 and 18, which are also indicated in FIG. 5.
An additional select transistor or an additional select diode for each memory cell is used to eliminate this problem. Proposals made in this connection are to be found, for example, in U.S. Pat. No. 5,640,343 and in the publication by S. S. P. Parkin et al., “Exchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory”, in Journal of Applied Physics 85, 5828–5833 (1999). However, the additional components increase the surface area taken up by each memory cell and also the complexity of the production process.
The publication by M. N. Kozicki et al., “Applications of programmable resistance changes in metal-doped chalcogenides”, in Electrochemical Society Proceedings 99–13, 298–309 (1999) has described a programmable metalization memory cell (PMC), which is suitable for use in programmable ROM components. A PMC of this type comprises a storage region formed from a chalcogenide glass, in particular arsenic sulfide or germanium selenide, which is doped, for example, with silver atoms. As an alternative to silver, it is also possible to use copper for the doping. The metal atoms are incorporated in the chalcogenide glass. In the unprogrammed state, a low electrical conductivity results, substantially on account of ion transport, so that the electrical resistance is high compared to typical metals. Undoped chalcogenides, such as GeSe or GeS, and Ag-doped chalcogenides are p-conducting.
A metal-doped chalcogenide glass is also referred to as a solid-state electrolyte. If electrodes are applied to a solid-state electrolyte of this type and a voltage is applied to the electrodes, positively charged metal ions migrate from the anode into the chalcogenide glass. Under suitable conditions, the ions are deposited in the chalcogenide glass in the form of a solid metallic deposit, which can ultimately extend from the cathode all the way to the anode. It is in this way possible to produce an electrically conductive connection formed from metal between the electrodes through the solid-state electrolyte. This process can be at least partially reversed by reversing the polarity of the applied electric voltage.
U.S. patent application Publication No. 2003/0193053 A1 describes a memory cell arrangement in cross-point architecture, in which the memory cells are formed by a programmable metalization memory cell with an associated thin-film diode. In the individual memory cell, there is a layer sequence, which includes at least a first layer of a chalcogenide glass, which is n-conductively doped for example with bismuth or lead, and a second layer of a chalcogenide glass, which is doped with silver and is p-conducting, between an interconnect, which represents a lower electrode and comprises, for example, aluminum or copper, and an upper electrode. The pn junction formed as a result is a diode that transmits current substantially in only one direction. It is also pointed out in this document that the diode, which is in each case connected in series with a memory cell of the array, should if possible also have an increased response threshold in the direction in which the current flows, in order to prevent accidental programming of the memory cell, but on the other hand in the blocking direction should have a certain transmission, so that when the contents of the memory are being read by applying a voltage in the blocking direction, a sufficient leakage current can be detected. The diodes integrated in these memory cells reduce the disturb effect of the memory cell arrangement as a whole.
The publication by A. V. Kolobov et al., “On the mechanism of photodoping in vitreous chalcogenides”, in Philosophical Magazine B 61 859–865 (1990) has described an investigation into the photodoping of chalcogenide glasses. The layer structures, which were investigated for this purpose, comprise As2S3, GeS2 and elemental selenium, as well as silver layers provided as electrodes. For the example of a GeS2 film provided with a silver electrode and an aluminum electrode and doped with silver, it is stated that a positive voltage at the silver electrode forces silver ions into the chalcogenide glass and increases the conductivity, whereas after the polarity of the voltage has been reversed the ions are extracted from the doped layer.